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ispLSI 1048C
(R)
In-System Programmable High Density PLD Features
* HIGH-DENSITY PROGRAMMABLE LOGIC -- 8000 PLD Gates -- 96 I/O Pins, 12 Dedicated Inputs, 2 Global Output Enables -- 288 Registers -- High-Speed Global Interconnect -- Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. -- Small Logic Block Size for Random Logic -- Security Cell Prevents Unauthorized Copying * HIGH PERFORMANCE E2CMOS(R) TECHNOLOGY -- fmax = 70 MHz Maximum Operating Frequency -- fmax = 50 MHz for Industrial and Military/883 Devices -- tpd = 16 ns Propagation Delay -- TTL Compatible Inputs and Outputs -- Electrically Erasable and Reprogrammable -- Non-Volatile E2CMOS Technology -- 100% Tested at Time of Manufacture * IN-SYSTEM PROGRAMMABLE -- In-System ProgrammableTM (ISPTM) 5-Volt Only -- Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality -- Reprogram Soldered Devices for Faster Debugging * COMBINES EASE OF USE AND THE FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS -- Complete Programmable Device Can Combine Glue Logic and Structured Designs -- Four Dedicated Clock Input Pins -- Synchronous and Asynchronous Clocks -- Flexible Pin Placement -- Optimized Global Routing Pool Provides Global Interconnectivity * ispDesignEXPERTTM - LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING -- Superior Quality of Results -- Tightly Integrated with Leading CAE Vendor Tools -- Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZERTM -- PC and UNIX Platforms
Functional Block Diagram
Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 A0 Output Routing Pool E7 E6 E5 E4 E3 E2 E1 E0 D7 D5
Output Routing Pool
A2 A3 A4 A5 A6 A7
Logic
DQ
U C SE O is Mp ML ER SI C 10 IA 4 D L 8E ES & A IG IN F N D OR SU ST N R EW IA L
DQ
Global Routing Pool (GRP)
Array
DQ
GLB
D4 D3 D2 D1 D0 CLK
B0 B1 B2 B3 B4 B5 B6 B7 Output Routing Pool
C0 C1 C2 C3 C4 C5 C6 C7 Output Routing Pool
0139G1A-isp
Description
The ispLSI 1048C is a High-Density Programmable Logic Device containing 288 Registers, 96 Universal I/O pins, 12 Dedicated Input pins, two Global Output Enables (GOE), four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1048C features 5-Volt in-system programming and in-system diagnostic capabilities. It is the first device which offers non-volatile reprogrammability of the logic, and the interconnect to provide truly reconfigurable systems. Compared to the ispLSI 1048, the ispLSI 1048C offers two additional dedicated inputs and two new Global Output Enable pins. The basic unit of logic on the ispLSI 1048C device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. F7 in figure 1. There are a total of 48 GLBs in the ispLSI 1048C devices. Each GLB has 18 inputs, a programmable AND/OR/XOR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device.
Copyright (c) 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
August 2000
1048C_08
1
Output Routing Pool
A1
DQ
D6
Specifications ispLSI 1048C
Functional Block Diagram
Figure 1. ispLSI 1048C Functional Block Diagram
I/O I/O I/O I/O 95 94 93 92 RESET
GOE0 GOE1
I/O I/O I/O I/O 91 90 89 88
I/O I/O I/O I/O 87 86 85 84
I/O I/O I/O I/O 83 82 81 80
IN IN 11 10
I/O I/O I/O I/O 79 78 77 76
I/O I/O I/O I/O 75 74 73 72
I/O I/O I/O I/O 71 70 69 68
I/O I/O I/O I/O 67 66 65 64
IN 9
IN 8
Input Bus Generic Logic Blocks (GLBs) F7 F6 Output Routing Pool (ORP) F5 F4 F3 F2 F1 F0 E7 E6
Input Bus Output Routing Pool (ORP) E5 E4 E3 E2 E1 E0
IN 7 IN 6 I/O 63 I/O 62 I/O 61 I/O 60
Output Routing Pool (ORP)
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 SDI/IN 0 MODE/IN 1
U C SE O is Mp ML ER SI C 10 IA 4 D L 8E ES & A IG IN F N D OR SU ST N R EW IA L
D7 A0 D6 D5 D4 D3 D2 D1 D0 A1 A2 A3 A4 A5 A6 A7
Output Routing Pool (ORP)
I/O 59 I/O 58 I/O 57
Global Routing Pool (GRP)
lnput Bus
I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48
Input Bus
B0
B1
B2
B3
B4
B5
B6
B7
C0
C1
C2
C3
C4
C5
C6
C7
Output Routing Pool (ORP) Input Bus
Output Routing Pool (ORP) Input Bus
Clock Distribution Network
CLK 0 CLK 1 CLK 2 IOCLK 0 IOCLK 1
Megablock
ispEN
IN2 SDO/ IN3
I/O I/O I/O I/O 16 17 18 19
I/O I/O I/O I/O 20 21 22 23
I/O I/O I/O I/O 24 25 26 27
I/O I/O I/O I/O 28 29 30 31
IN SCLK/ I/O I/O I/O I/O 4 IN 5 32 33 34 35
I/O I/O I/O I/O 36 37 38 39
I/O I/O I/O I/O 40 41 42 43
I/O I/O I/O I/O 44 45 46 47
YYYY 0123
0139F(2)-48B-isp
The device also has a 96 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, registered input, latched input, output or bi-directional I/O pin with 3-state control. Additionally, all outputs have selectable polarity, active high or active low. The signal voltage levels are TTL-compatible, and the output drivers can source 4 mA or sink 8 mA. Eight GLBs, 16 I/O cells, two dedicated inputs and one ORP are connected together to make a Megablock as shown in figure 1. The outputs of the eight GLBs are connected to a set of 16 universal I/O cells by the ORP. Each ispLSI 1048C device contains six Megablocks.
The GRP has, as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 1048C device are selected using the Clock Distribution Network. Four dedicated clock pins (Y0, Y1, Y2 and Y3) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (D0 on the ispLSI 1048C device). The logic of this GLB allows the user to create an internal clock from a combination of internal signals.
2
Specifications ispLSI 1048C
Absolute Maximum Ratings 1
Supply Voltage Vcc .................................. -0.5 to +7.0V Input Voltage Applied ........................ -2.5 to VCC +1.0V Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V Storage Temperature ................................ -65 to 150C Case Temp. with Power Applied .............. -55 to 125C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
SYMBOL PARAMETER
U C SE O is Mp ML ER SI C 10 IA 4 D L 8E ES & A IG IN F N D OR SU ST N R EW IA L
MIN. 4.75 4.5 4.5 0 MAX. 5.25 5.5 5.5 0.8 Commercial Industrial TA = 0C to +70C Supply Voltage TA = -40C to +85C Military/883 TC = -55C to +125C Input Low Voltage Input High Voltage 2.0 Vcc + 1
PARAMETER MAXIMUM1 8 UNITS pf Dedicated Input Capacitance Commercial/Industrial Military 10 pf I/O and Clock Capacitance 10 pf
PARAMETER MINIMUM 20 10000 MAXIMUM -- --
Max. Junction Temp. (TJ) with Power Applied ... 150C
UNITS
VCC VIL VIH
V
V V
Table 2- 0005Aisp w/mil.eps
Capacitance (TA=25oC, f=1.0 MHz)
SYMBOL
TEST CONDITIONS VCC=5.0V, VIN=2.0V VCC=5.0V, VIN=2.0V VCC=5.0V, VI/O, VY=2.0V
Table 2- 0006
C1 C2
1. Characterized but not 100% tested.
Data Retention Specifications
UNITS Years Cycles
Table 2- 0008B
Data Retention Erase/Reprogram Cycles
3
Specifications ispLSI 1048C
Switching Test Conditions
Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load GND to 3.0V 3ns 10% to 90% 1.5V 1.5V See figure 2
Figure 2. Test Load
+ 5V R1 Device Output R2 CL* Test Point
Output Load Conditions (see figure 2)
Test Condition A B R1
Active High Active Low
C
Active High to Z at VOH - 0.5V Active Low to Z at VOL + 0.5V
DC Electrical Characteristics
SYMBOL
U C SE O is Mp ML ER SI C 10 IA 4 D L 8E ES & A IG IN F N D OR SU ST N R EW IA L
Table 2- 0003
3-state levels are measured 0.5V from steady-state active level.
R2
CL
*CL includes Test Fixture and Probe Capacitance.
470
390 390
35pF 35pF 35pF 5pF

470
390 390
470
390
5pF
Table 2- 0004A
Over Recommended Operating Conditions
CONDITION
PARAMETER
MIN. - - - - - - - - 2.4
TYP.3 - - - - - - -
MAX. 0.4 -
UNITS V V A A A A mA mA mA
VOL VOH IIL IIH IIL-isp IIL-PU IOS1 ICC2,4
Output Low Voltage
IOL =8 mA
Output High Voltage
IOH =-4 mA
Input or I/O Low Leakage Current 0V VIN VIL (MAX.) Input or I/O High Leakage Current 3.5V VIN VCC I/O Active Pull-Up Current 0V VIN VIL ispEN Input Low Leakage Current 0V VIN VIL (MAX.) Output Short Circuit Current
-10 10
-150 -150 -200 235 260
VCC = 5V, VOUT = 0.5V fTOGGLE = 1 MHz
Operating Power Supply Current
VIL = 0.5V, VIH = 3.0V Commercial
165 165
Industrial/Military
1. One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using twelve 16-bit counters. 3. Typical values are at VCC = 5V and TA = 25oC. 4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum Table 2- 0007A-48-isp ICC.
4
Specifications ispLSI 1048C
External Timing Parameters
Over Recommended Operating Conditions
42 PARAMETER TEST #
COND.
DESCRIPTION1 Data Propagation Delay, 4PT bypass, ORP bypass Data Propagation Delay Clock Frequency with Internal Feedback3 - -
-70
16.0 19.0 - - - - - -
-50
22.0 26.0 - - - -
UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN. MAX. MIN. MAX. 1 2 3
U C SE O is Mp ML ER SI C 10 IA 4 D L 8E ES & A IG IN F N D OR SU ST N R EW IA L
- - 83.3 9.5 - 0 58.8 13.0 - 0 6 7 8 9 GLB Reg. Setup Time before Clock, 4PT bypass GLB Reg. Clock to Output Delay, ORP bypass GLB Reg. Hold Time after Clock, 4 PT bypass GLB Reg. Setup Time before Clock A - - - - 10.0 - - 11.0 - 0 - 15.0 - 0 - 10 GLB Reg. Clock to Output Delay 11 GLB Reg. Hold Time after Clock 12 Ext. Reset Pin to Output Delay 13 Ext. Reset Pulse Duration 14 Input to Output Enable 11.5 - A - 15.0 - 10.0 - - - - 13.5 - - - - B 20.0 20.0 15.0 15.0 - - - - C B 15 Input to Output Disable 16 Global OE Output Enable C - - - - 17 Global OE Output Disable 20 Ext. Sync. Clock Pulse Duration, High 21 Ext. Sync. Clock Pulse Duration, Low 6.0 6.0 2.0 6.5 8.5 8.5 3.0 9.0 22 I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3) 23 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
tpd1 tpd2 fmax (Int.) fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl tsu3 th3
1. 2. 3. 4.
A A A -
70.4 47.6
50.3 34.5
1 4 Clock Frequency with External Feedback ( tsu2 + tco1 ) 1 5 Clock Frequency, Max Toggle ( twh + tw1 )
14.0 - -
16.0 -
20.5 -
27.5 27.5 20.5 20.5 - - - -
Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-Bit counter using GRP feedback. Reference Switching Test Conditions section.
Table 2- 0030-48C/70, 50
5
Specifications ispLSI 1048C
Internal Timing Parameters1
2
PARAMETER
#
DESCRIPTION
-70
-50
UNITS
MIN. MAX. MIN. MAX.
Inputs tiobp tiolat tiosu tioh tioco tior tdin GRP tgrp1 tgrp4 tgrp8 tgrp16 tgrp48 GLB t4ptbp t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck ORP torp torpbp
24 25 26 27 28 29 30
I/O Register Bypass I/O Latch Delay I/O Register Setup Time before Clock I/O Register Hold Time after Clock I/O Register Clock to Out Delay
- - 6.5 0.1 - - -
3.1 4.0 - -
- - 9.1 0.3 - - -
4.3 5.5 - - 4.6 5.1 7.4
ns ns ns ns ns ns ns
U C SE O is Mp ML ER SI C 10 IA 4 D L 8E ES & A IG IN F N D OR SU ST N R EW IA L
3.4 3.7 5.4 I/O Register Reset to Out Delay Dedicated Input Delay 31 32 33 34 35 GRP Delay, 1 GLB Load - - - - - 4.5 4.9 5.8 7.6 - - - - - GRP Delay, 4 GLB Loads GRP Delay, 8 GLB Loads GRP Delay, 16 GLB Loads GRP Delay, 48 GLB Loads 16.5 36 37 38 39 40 41 42 43 44 45 46 47 4 Product Term Bypass Path Delay 1 Product Term/XOR Path Delay - - - - - 4.0 4.9 5.5 6.5 0.9 - - - - - - - 20 Product Term/XOR Path Delay XOR Adjacent Path Delay3 GLB Register Bypass Delay GLB Register Setup Time before Clock GLB Register Hold Time after Clock 2.9 5.3 - - - - 3.9 7.3 - - - - GLB Register Clock to Output Delay 1.5 2.1 8.1 7.0 6.0 GLB Register Reset to Output Delay GLB Product Term Reset to Register Delay GLB Product Term Output Enable to I/O Cell Delay GLB Product Term Clock Delay 2.5 3.4 48 49 ORP Delay ORP Bypass Delay - - 2.5 1.0 - -
6.2 6.7 8.0 10.5 22.7
ns ns ns ns ns
5.5 6.7 7.5 8.9 1.2 - - 2.3 2.8 11.1 9.6 8.2
ns ns ns ns ns ns ns ns ns ns ns ns
3.4 1.4
ns ns
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros.
Table 2- 0036-48C/70, 50
6
Specifications ispLSI 1048C
Internal Timing Parameters1
2
PARAMETER
#
DESCRIPTION
-70
-50
UNITS
MIN. MAX. MIN. MAX.
U C SE O is Mp ML ER SI C 10 IA 4 D L 8E ES & A IG IN F N D OR SU ST N R EW IA L
Global OE - 10.0 - Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) Clock Delay, Y1 or Y2 to Global GLB Clock Line 5.4 4.5 1.9 4.5 1.9 5.4 6.4 5.5 6.4 5.5 7.4 6.1 2.6 6.1 2.6 Clock Delay, Clock GLB to Global GLB Clock Line Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line Clock Delay, Clock GLB to I/O Cell Global Clock Line Global Reset to GLB and I/O Registers - 8.3 -
Outputs tob 50 toen 51 todis 52 tgoe 53 Clocks tgy0 54 tgy1/2 55 tgcp 56 tioy2/3 57 tiocp 58 Global Reset tgr 59
Output Buffer Delay I/O Cell OE to Output Enabled I/O Cell OE to Output Disabled
- - -
2.1 5.0 5.0
- - -
2.9 6.9 6.9 13.6
ns ns ns ns
7.4 8.7 7.6 8.7 7.6
ns ns ns ns ns
11.4
ns
1. Internal Timing Parameters are not tested and are for reference only.
Table 2- 0037-48C/70, 50
7
Specifications ispLSI 1048C
ispLSI 1048C Timing Model
I/O Cell GRP Feedback Ded. In GLB ORP I/O Cell
#30 I/O Reg Bypass #24 Input D Register Q RST #25 - 29 GRP 4 #32 GRP Loading Delay #31, 33, 34, 35 4 PT Bypass #36 20 PT XOR Delays #37, 38, 39 #59 D RST GLB Reg Bypass #40 GLB Reg Delay Q #41, 42, 43, 44 ORP Bypass #49 ORP Delay #48 #50 I/O Pin (Output) #51, 52
I/O Pin (Input)
#59 Reset
Y1,2,3
Y0 GOE0, 1
U C SE O is Mp ML ER SI C 10 IA 4 D L 8E ES & A IG IN F N D OR SU ST N R EW IA L
Clock Distribution #55, 56, 57, 58 #54 Control RE PTs OE #45, 46, CK 47 #53
0491A/48
Derivations of tsu, th and tco from the Product Term Clock1
tsu
= Logic + Reg su - Clock (min) = (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min)) = (#24 + #32 + #38) + (#41) - (#24 + #32 + #47) 5.9 ns = (3.1 + 4.9 + 5.5) + (2.9) - (3.1 + 4.9 + 2.5) = Clock (max) + Reg h - Logic = (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) = (#24 + #32 + #47) + (#42) - (#24 + #32 + #38 ) 5.8 ns = (3.1 + 4.9 + 6.0) + (5.3) - (3.1 + 4.9 + 5.5)
th
tco
= Clock (max) + Reg co + Output = (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + = (#24 + #32 + #47) + (#43) + (#48 + #50) 20.1 ns = (3.1 + 4.9 +6.0) + (1.5) + (2.5 + 2.1)
tob)
Derivations of tsu, th and tco from the Clock GLB1
tsu
= Logic + Reg su - Clock (min) = (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + = (#24 + #32 + #38) + (#41) - (#54 + #43 + #56) 7.6 ns = (3.1 + 4.9 + 5.5) + (2.9) - (5.4 + 1.5 + 1.9)
tgco + tgcp(min))
th
= Clock (max) + Reg h - Logic = (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) = (#54 + #43 + #56) + (#42) - (#24 + #32 + #38) 4.2 ns = (5.4 + 1.5 + 5.5) + (5.3) - (3.1 + 4.9 + 5.5)
tco
= Clock (max) + Reg co + Output = (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + = (#54 + #43 + #56) + (#43) + (#48 + #50) 18.5 ns = (5.4 + 1.5 + 5.5) + (1.5) + (2.5 + 2.1)
tob)
1. Calculations are based upon timing specifications for the ispLSI 1048C-70
Table 2- 0042-48C
8
Specifications ispLSI 1048C
Maximum GRP Delay vs GLB Loads
11 ispLSI 1048C-50 10 9
GRP Delay (ns)
8 7 6 5 4 3
ispLSI 1048C-70
Power Consumption
Power consumption in the ispLSI 1048C device depends on two primary factors: the speed at which the device is operating, and the number of Product Terms used. Fig-
ICC (mA)
Figure 3. Typical Device Power Consumption vs fmax 250 ispLSI 1048C 200
150 100 50
ICC can be estimated for the ispLSI 1048C using the following equation: ICC = 73 + (# of PTs * 0.23) + (# of nets * Max. freq * 0.010) where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max. freq = Highest Clock Frequency to the device
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 2 GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. 0127A-48C-80-isp
U C SE O is Mp ML ER SI C 10 IA 4 D L 8E ES & A IG IN F N D OR SU ST N R EW IA L
1 4 8 12 16 GLB Loads
0126A-48C-80-isp
ure 3 shows the relationship between power and operating speed.
0
10
20
30
40
50
60
70
80
fmax (MHz)
Notes: Configuration of Twelve 16-bit Counters Typical Current at 5V, 25C
9
Specifications ispLSI 1048C
Pin Description
NAME
I/O 0 - I/O 5 I/O 6 - I/O 11 I/O 12 - I/O 17 I/O 18 - I/O 23 I/O 24 - I/O 29 I/O 30 - I/O 35 I/O 36 - I/O 41 I/O 42 - I/O 47 I/O 48 - I/O 53 I/O 54 - I/O 59 I/O 60 - I/O 65 I/O 66 - I/O 71 I/O 72 - I/O 77 I/O 78 - I/O 83 I/O 84 - I/O 89 I/O 90 - I/O 95 GOE0, GOE1 IN 2, IN 4 IN 6 - IN 11 ispEN
PQFP PIN NUMBERS
21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 34, 35, 36, 37, 38, 40, 41, 42, 43, 44, 52, 53, 54, 55, 56, 58, 59, 60, 61, 62, 66, 67, 68, 69, 70, 72, 73, 74, 75, 76, 85, 86, 87, 88, 89, 91, 92, 93, 94, 95, 98, 99,100,101,102, 104,105,106,107,108, 117,118,119,120,121, 123,124,125,126,127, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 64, 114 26 32 39 45 57 63 71 77 90 96 103 109 122 128 7 13
DESCRIPTION
Input/Output Pins - These are the general purpose I/O pins used by the logic array.
SDI/IN 01
MODE/IN 11
SDO/IN 31
SCLK/IN 51
RESET Y0 Y1
Y2
Y3
GND VCC
1. Pins have dual function capability.
U C SE O is Mp ML ER SI C 10 IA 4 D L 8E ES & A IG IN F N D OR SU ST N R EW IA L
Global output enables for all I/Os. 47, 51 84,110,111, 115,116, 14 18 Dedicated input pins to the device. 20 46 50 78 19 15 83 80 79 1, 17, 33, 49, 65, 81 97, 112 16, 48, 82, 113 Ground (GND) VCC
Input - Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK options become active. Input - This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI/IN 0 also is used as one of the two control pins for the isp state machine. Input - This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as a pin to control the operation of the isp state machine. Input/Output - This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an output pin to read serial shift register data. Input - This pin performs two functions. It is a dedicated input when ispEN is logic high. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. Dedicated clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB on the device. Dedicated clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB and/or any I/O cell on the device. Dedicated clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any I/O cell on the device.
Table 2- 0002C-48C
10
Specifications ispLSI 1048C
Pin Description
NAME
I/O 0 - I/O 5 I/O 6 - I/O 11 I/O 12 - I/O 17 I/O 18 - I/O 23 I/O 24 - I/O 29 I/O 30 - I/O 35 I/O 36 - I/O 41 I/O 42 - I/O 47 I/O 48 - I/O 53 I/O 54 - I/O 59 I/O 60 - I/O 65 I/O 66 - I/O 71 I/O 72 - I/O 77 I/O 78 - I/O 83 I/O 84 - I/O 89 I/O 90 - I/O 95 GOE0, GOE1 IN 2, IN 4 IN 6 - IN 11 ispEN
CPGA PIN NUMBERS
J2, L2, M3, P4, N9, N11, M12, L14, F13, D13, C12, A11, B6, B4, C3, D1, N13, P7, F14, J3, K3, P2, M5, M9, M10, N14, K12, F12, E12, A13, C10, C6, C5, B1, E3, K1, N1, N3, N5, P10, P13, M13, K13, E14, B14, B12, B10, A5, A2, C2, E2, L1, M2, M4, P5, P11, N12, L12, K14, D14, C13, C11, A10, A4, B3, D3, E1, K2, L3, P3, M6, N10, M11, M14, J12, E13, D12, A12, C9, B5, C4, C1, F3, M1, P1, N4, N6, P12, P14, L13, J13, C14, A14, B11, B9, A3, A1, D2, F2
DESCRIPTION
Input/Output Pins - These are the general purpose I/O pins used by the logic array.
SDI/IN 01
MODE/IN 11
SDO/IN 31
SCLK/IN 51
RESET Y0 Y1
Y2
Y3
GND VCC
1. Pins have dual function capability.
U C SE O is Mp ML ER SI C 10 IA 4 D L 8E ES & A IG IN F N D OR SU ST N R EW IA L
B7, Global output enables for all I/Os. P9 A9, Dedicated input pins to the device. A8, A7, A6, F1 H2 J1 P6 P8 J14 H1 G1 G14 H13 H14 B2, M8, C7, N7 B8, B13, C8, H3, H12, N2, N8 G2, G3, G12, G13, M7, Ground (GND) VCC
Input - Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK options become active. Input - This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI/IN 0 also is used as one of the two control pins for the isp state machine. Input - This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as a pin to control the operation of the isp state machine. Input/Output - This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an output pin to read serial shift register data. Input - This pin performs two functions. It is a dedicated input when ispEN is logic high. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. Dedicated clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB on the device. Dedicated clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB and/ or any I/O cell on the device. Dedicated clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any I/O cell on the device.
Table 2- 0002C-48C/CPGA
11
Specifications ispLSI 1048C
Pin Configuration
ispLSI 1048C 128-Pin PQFP Pinout Diagram
I/O 83 I/O 82 I/O 81 I/O 80 I/O 79 I/O 78 I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 IN 10 IN 9 GOE 1 VCC GND IN 8 IN 7 I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64 I/O 63 I/O 62 I/O 61 I/O 60 GND 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97
U C SE O is Mp ML ER SI C 10 IA 4 D L 8E ES & A IG IN F N D OR SU ST N R EW IA L
ispLSI 1048C
Top View
1. Pins have dual function capability.
GND I/O 84 I/O 85 I/O 86 I/O 87 I/O 88 I/O 89 I/O 90 I/O 91 I/O 92 I/O 93 I/O 94 I/O 95 IN11 Y0 VCC GND ispEN RESET 1 SDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
I/O 59 I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 IN 6 Y1 VCC GND Y2 Y3 IN 5/SCLK1 I/O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 I/O 38 I/O 37 I/O 36 GND
GND I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 1 MODE/IN 1 IN 2 VCC GND 1 SDO/IN 3 IN 4 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 35 GOE 0
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
0124-48C
12
Specifications ispLSI 1048C
Pin Configuration
ispLSI 1048C 133-Pin CPGA Pinout Diagram
14
I/O59
13
I/O61
12
I/O64
11
I/O66
10
I/O69
9
IN7
8
IN8
7
IN9
6
IN10
5
I/O74
4
I/O75
3
I/O77
2
I/O80
1
I/O83
PIN A1
A
I/O56
GND
I/O62
I/O65
I/O68
I/O71
GND
GOE1
I/O72
I/O76
I/O78
I/O81
GND
I/O85
B
I/O53
U C SE O is Mp ML ER SI C 10 IA 4 D L 8E ES & A IG IN F N D OR SU ST N R EW IA L
I/O57 I/O60 I/O63 I/O67 I/O70 GND Vcc I/O73 I/O79 I/O82 I/O84 I/O86 I/O54 I/O58 INDEX I/O87 I/O89 I/O52 I/O55 I/O91 I/O92 I/O48 I/O49 I/O94 I/O95 Vcc Vcc
I/O88
C
I/O51
I/O90
D
I/O50
I/O93
E
IN6
IN11
F
Y1
ispLSI 1048C/883
Bottom View
Vcc
Vcc
Y0
G
Y3
Y2
GND
GND
ispEN
RESET
H
SCLK/ IN51
I/O47
I/O46
I/O1
I/O0
SDI/ IN01
J
I/O45
I/O44
I/O43
I/O7
I/O4
I/O2
K
I/O42
I/O41
I/O39
I/O10
I/O6
I/O3
L
I/O40
I/O38
I/O36
I/O34
I/O31
I/O25
GND
Vcc
I/O22
I/O19
I/O15
I/O12
I/O9
I/O5
M
I/O37
GOE0
I/O33
I/O30
I/O28
I/O24
GND
Vcc
I/O23
I/O20
I/O17
I/O14
GND
I/O8
N
I/O35
I/O32
I/O29
I/O27
I/O26
IN4
SDO/ IN31
IN2
MODE/ IN11
I/O21
I/O18
I/O16
I/O13
I/O11
P
1. Pins have dual function capability.
133 CPGA Pinout.eps
13
Specifications ispLSI 1048C
Part Number Description
ispLSI 1048C -- XX
Device Family
X
X
X
Grade Blank = Commercial I = Industrial /883 = 883 Military Process Package Q = PQFP G = CPGA Power L = Low
Device Number Speed 70 = 70 MHz fmax 50 = 50 MHz fmax
Ordering Information
Family ispLSI
U C SE O is Mp ML ER SI C 10 IA 4 D L 8E ES & A IG IN F N D OR SU ST N R EW IA L
0212-80B-isp1048C
COMMERCIAL
Family ispLSI
fmax (MHz) tpd (ns)
70 50 16
Ordering Number
Package
ispLSI 1048C-70LQ
128-Pin PQFP 128-Pin PQFP
22
ispLSI 1048C-50LQ
INDUSTRIAL
Family ispLSI
fmax (MHz) tpd (ns)
50 22
Ordering Number
Package
ispLSI 1048C-50LQI
128-Pin PQFP
MILITARY
fmax (MHz) tpd (ns)
50 22
Ordering Number
SMD Number
Package
ispLSI 1048C-50LG/883
5962-9558701MXC
133-Pin CPGA
Table 2- 0041A-48C-isp
14

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